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A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip.

C. Lin, W. He, Y. Sun, L. Shao, B. Zhang, J. Yang, and M. Seok. IEEE J. Solid State Circuits, 59 (2): 616-625 (February 2024)

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Weifeng Song

Weifeng Shi

Weifeng Shang

Hongxia He

Ning He

Other publications of authors with the same name

Near- and Sub-Vt Pipelines Based on Wide-Pulsed-Latch Design Techniques.W. Jin, S. Kim, W. He, Z. Mao, and M. Seok. IEEE J. Solid State Circuits, 52 (9): 2475-2487 (2017)A hardware-friendly hierarchical HEVC motion estimation algorithm for UHD applications.L. Hu, J. Gu, G. He, and W. He. ISCAS, page 1-4. IEEE, (2017)A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead.H. Zhang, W. He, Y. Sun, and M. Seok. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (3): 1015-1028 (March 2023)Surface stress monitoring of laser shock peening using AE time-scale texture image and multi-scale blueprint separable convolutional networks with attention mechanism.R. Qin, Z. Zhang, J. Huang, J. Wang, Z. Du, G. Wen, and W. He. Expert Syst. Appl., (August 2023)Multi-Label Classification of Fundus Images With EfficientNet.J. Wang, L. Yang, Z. Huo, W. He, and J. Luo. IEEE Access, (2020)A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing.Z. Liang, D. Lv, C. Cui, H. Chen, W. He, W. Sheng, N. Jing, Z. Mao, and G. He. IEEE Trans. Very Large Scale Integr. Syst., 29 (2): 307-320 (2021)A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router.B. Pei, S. Xu, Z. Luo, Q. Wang, M. Lai, and W. He. IEEE Trans. Circuits Syst. II Express Briefs, 70 (10): 3787-3791 (October 2023)An efficient VLSI architecture for extended variable block sizes motion estimation.W. He, W. Chen, and Z. Mao. SoCC, page 347-350. IEEE, (2010)Monolithic 3D Carbon Nanotube Memory for Enhanced Yield and Integration Density.Y. Sun, W. He, Z. Mao, H. Jiao, and V. Kursun. IEEE Trans. Circuits Syst. I Regul. Pap., 67-I (7): 2431-2441 (2020)A Ternary Memristive Logic-in-Memory Design for Fast Data Scan.T. Shen, Y. Sun, W. He, Z. Li, W. Liu, Z. He, and L. Jiang. ICTA, page 183-184. IEEE, (2021)

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Disambiguation of "He, Weifeng"