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Disambiguation of "Sakurai, Takayasu"

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A high-speed, low-power capacitive-coupling transceiver for wireless wafer-level testing systems.

, , , , and . 3DIC, page 1-4. IEEE, (2010)

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Yoriko Sakurai

Kaneaki Sakurai

Takayasu Shimizu

Miriam Takayasu

 

Other publications of authors with the same name

Reducing IR drop in 3D integration to less than 1/4 using Buck Converter on Top die (BCT) scheme., , , , , , , and . ISQED, page 210-215. IEEE, (2013)Ambient electronics and ultra-low power LSI design.. VLSI-DAT, page 1-31. IEEE, (2012)High-Speed Circuit Design with Scaled-Down MOSFET's and Low Supply Voltage.. ISCAS, page 1487-1490. IEEE, (1993)A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping., , , and . ISSCC, page 358-608. IEEE, (2007)A 95mV-startup step-up converter with Vth-tuned oscillator by fixed-charge programming and capacitor pass-on scheme., , , , , , , , and . ISSCC, page 216-218. IEEE, (2011)A 80-mV input, fast startup dual-mode boost converter with charge-pumped pulse generator for energy harvesting., , , , , , and . A-SSCC, page 33-36. IEEE, (2011)Digital Active Gate Drive with Optimal Switching Patterns to Adapt to Sinusoidal Output Current in a Full Bridge Inverter Circuit., , , , , , , and . IECON, page 1684-1689. IEEE, (2019)An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS., , , and . ASP-DAC, page 109-110. IEEE, (2011)A low voltage buck DC-DC converter using on-chip gate boost technique in 40nm CMOS., , , , , , , and . ASP-DAC, page 109-110. IEEE, (2013)0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS., , , , , , , and . CICC, page 1-4. IEEE, (2010)