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A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS.

D. Yoo, M. Bagherbeik, W. Rahman, A. Sheikholeslami, H. Tamura, and T. Shibasaki. ISSCC, page 126-128. IEEE, (2019)

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Claudia Tamura

Ichiro Tamura

Hitoshi Tamura

Hirotaka Wakatsuki

Hirotaka Yoshida

Other publications of authors with the same name

Optimizing effective interconnect capacitance for FPGA power reduction.S. Huda, J. Anderson, and H. Tamura. FPGA, page 11-20. ACM, (2014)A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS.Y. Tomita, H. Tamura, M. Kibune, J. Ogawa, K. Gotoh, and T. Kuroda. IEEE J. Solid State Circuits, 42 (3): 627-636 (2007)A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique.Y. Okaniwa, H. Tamura, M. Kibune, D. Yamazaki, T. Cheung, J. Ogawa, N. Tzartzanis, W. Walker, and T. Kuroda. IEEE J. Solid State Circuits, 40 (8): 1680-1687 (2005)An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection.M. Jalali, R. Shivnaraine, A. Sheikholeslami, M. Kibune, and H. Tamura. CICC, page 1-8. IEEE, (2013)Charge recycling for power reduction in FPGA interconnect.S. Huda, J. Anderson, and H. Tamura. FPL, page 1-8. IEEE, (2013)Jitter injection for on-chip jitter measurement in PI-based CDRs.J. Liang, A. Sheikholeslami, H. Tamura, and H. Yamaguchi. CICC, page 1-4. IEEE, (2017)A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE.C. Ting, M. Jalali, A. Sheikholeslami, M. Kibune, and H. Tamura. CICC, page 1-4. IEEE, (2014)A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process.Y. Doi, S. Masaki, T. Chiba, H. Higashi, H. Yamaguchi, H. Takauchi, H. Ishida, K. Gotoh, J. Ogawa, and H. Tamura. CICC, page 131-134. IEEE, (2005)Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI.M. van Ierssel, H. Yamaguchi, A. Sheikholeslami, H. Tamura, and W. Walker. IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (5): 1306-1315 (2008)An 8-11 Gb/s Reference-Less Bang-Bang CDR Enabled by "Phase Reset".R. Shivnaraine, M. Jalali, A. Sheikholeslami, M. Kibune, and H. Tamura. IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (7): 2129-2138 (2014)

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Disambiguation of "Tamura, Hirotaka"

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A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS.

Please choose a person to relate this publication to

Claudia Tamura

Ichiro Tamura

Hitoshi Tamura

Hirotaka Wakatsuki

Hirotaka Yoshida

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Tamura, Hirotaka"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS.

Please choose a person to relate this publication to

Claudia Tamura

Ichiro Tamura

Hitoshi Tamura

Hirotaka Wakatsuki

Hirotaka Yoshida

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS.