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Seed Ordering and Selection for High Quality Delay Test.

T. Yoneda, M. Inoue, A. Taketani, and H. Fujiwara. Asian Test Symposium, page 313-318. IEEE Computer Society, (2010)

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Tomokazu Hattori

Tomokazu Nambu

Michiko Yoneda

Other publications of authors with the same name

An ECC-based memory architecture with online self-repair capabilities for reliability enhancement.G. Mayuga, Y. Yamato, T. Yoneda, M. Inoue, and Y. Sato. ETS, page 1-6. IEEE, (2015)Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects.T. Yoneda, and H. Fujiwara. DATE, page 1366-1369. ACM, (2008)DART: Dependable VLSI test architecture and its implementation.Y. Sato, S. Kajihara, T. Yoneda, K. Hatayama, M. Inoue, Y. Miura, S. Untake, T. Hasegawa, M. Sato, and K. Shimamura. ITC, page 1-10. IEEE Computer Society, (2012)A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation.Y. Yamato, T. Yoneda, K. Hatayama, and M. Inoue. ITC, page 1-8. IEEE Computer Society, (2012)Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses.F. Hussin, T. Yoneda, A. Orailoglu, and H. Fujiwara. ASP-DAC, page 720-725. IEEE Computer Society, (2007)Aging test strategy and adaptive test scheduling for SoC failure prediction.H. Yi, T. Yoneda, M. Inoue, Y. Sato, S. Kajihara, and H. Fujiwara. IOLTS, page 21-26. IEEE Computer Society, (2010)Detecting hardware Trojans without a Golden IC through clock-tree defined circuit partitions.F. Hossain, T. Yoneda, M. Inoue, and A. Orailoglu. ETS, page 1-6. IEEE, (2017)Test pattern selection to optimize delay test quality with a limited size of test set.M. Inoue, A. Taketani, T. Yoneda, H. Iwata, and H. Fujiwara. European Test Symposium, page 260. IEEE Computer Society, (2010)Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing.F. Hussin, T. Yoneda, and H. Fujiwara. ATS, page 459-462. IEEE, (2007)Power-constrained test scheduling for multi-clock domain SoCs.T. Yoneda, K. Masuda, and H. Fujiwara. DATE, page 297-302. European Design and Automation Association, Leuven, Belgium, (2006)

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Disambiguation of "Yoneda, Tomokazu"

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Seed Ordering and Selection for High Quality Delay Test.

Please choose a person to relate this publication to

Tomokazu Hattori

Tomokazu Nambu

Michiko Yoneda

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yoneda, Tomokazu"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Seed Ordering and Selection for High Quality Delay Test.

Please choose a person to relate this publication to

Tomokazu Hattori

Tomokazu Nambu

Michiko Yoneda

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Seed Ordering and Selection for High Quality Delay Test.