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First demonstration of Two Metal Level Semi-damascene Interconnects with Fully Self-aligned Vias at 18MP., , , , , , , , , and 5 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2022)A tool flow for predicting system level timing failures due to interconnect reliability degradation., , , , , and . ACM Great Lakes Symposium on VLSI, page 291-296. ACM, (2008)Layout dependency induced deviation from Poisson area scaling in BEOL dielectric reliability., , , , and . Microelectron. Reliab., 45 (9-11): 1299-1304 (2005)Electromigration limits of copper nano-interconnects., , , and . IRPS, page 1-6. IEEE, (2021)Global Is the New Local: FPGA Architecture at 5nm and Beyond., , , and . FPGA, page 34-44. ACM, (2021)Metal reliability mechanisms in Ruthenium interconnects., , , , , , , , and . IRPS, page 1-7. IEEE, (2020)Low-Frequency Noise Measurements to Characterize Cu-Electromigration Down to 44nm Metal Pitch., , , , and . IRPS, page 1-6. IEEE, (2019)Stress mitigation of 3D-stacking/packaging induced stresses., , , , , , , , and . IRPS, page 4. IEEE, (2018)Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access., , , , , , , and . ISQED, page 1. IEEE, (2023)Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects., , , , , , , , , and 1 other author(s). Microelectron. Reliab., (2017)