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Disambiguation of "Zambreno, Joseph"

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Scheduling Challenges in Mixed Critical Real-Time Heterogeneous Computing Platforms.

, , , , , and . ICCS, volume 18 of Procedia Computer Science, page 1891-1898. Elsevier, (2013)

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Stefanie Joseph

Julie Joseph

Virginia Joseph

Joseph Kugbe

Joseph Landsberg

 

Other publications of authors with the same name

SAIDuCANT: Specification-Based Automotive Intrusion Detection Using Controller Area Network (CAN) Timing., , , and . IEEE Trans. Vehicular Technology, 69 (2): 1484-1494 (2020)A Reconfigurable Architecture for the Detection of Strongly Connected Components., , , and . ACM Trans. Reconfigurable Technol. Syst., 9 (2): 16:1-16:19 (2016)An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (1): 113-123 (2012)Scalable FastMDP for Pre-departure Airspace Reservation and Strategic De-conflict., , and . CoRR, (2020)RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing., , , , and . IEEE Trans. Parallel Distributed Syst., 27 (10): 3029-3043 (2016)Towards Reverse Engineering Controller Area Network Messages Using Machine Learning., , and . WF-IoT, page 1-6. IEEE, (2020)An FPGA-based Hardware Accelerator for Iris Segmentation., , and . ReConFig, page 1-8. IEEE, (2018)k-NN text classification using an FPGA-based sparse matrix vector multiplication accelerator., , , , , and . EIT, page 257-263. IEEE, (2015)Exploring Area/Delay Tradeoffs in an AES FPGA Implementation., , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 575-585. Springer, (2004)Design and Implementation of an FPGA Architecture for High-Speed Network Feature Extraction., , , , and . FPT, page 49-56. IEEE, (2007)