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Disambiguation of "Vyas, Sudhanshu"

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Scheduling Challenges in Mixed Critical Real-Time Heterogeneous Computing Platforms.

, , , , , and . ICCS, volume 18 of Procedia Computer Science, page 1891-1898. Elsevier, (2013)

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Sudhanshu Dole

Sandra Vyas

Mukesh Kumar Vyas

Nadine Vyas

Avinash Vyas

 

Other publications of authors with the same name

Improving System Predictability and Performance via Hardware Accelerated Data Structures., , , , , , and . ICCS, volume 9 of Procedia Computer Science, page 1197-1205. Elsevier, (2012)A Fault-Aware Toolchain Approach for FPGA Fault Tolerance., , and . ACM Trans. Design Autom. Electr. Syst., 20 (2): 32:1-32:22 (2015)Cache design for mixed criticality real-time systems., , , , , and . ICCD, page 513-516. IEEE Computer Society, (2014)A software configurable coprocessor-based state-space controller., , , , and . FPL, page 1-6. IEEE, (2015)Design and evaluation of a delay-based FPGA Physically Unclonable Function., , , , , and . ICCD, page 143-146. IEEE Computer Society, (2012)Hardware-software architecture for priority queue management in real-time and embedded systems., , , , , and . Int. J. Embed. Syst., 6 (4): 319-334 (2014)Team IiSsUu0-24 design overview: MEMOCODE 2010 design contest., , , , , , , , , and 1 other author(s). MEMOCODE, page 99-102. IEEE Computer Society, (2010)Scheduling Challenges in Mixed Critical Real-Time Heterogeneous Computing Platforms., , , , , and . ICCS, volume 18 of Procedia Computer Science, page 1891-1898. Elsevier, (2013)An FPGA-Based Plant-on-Chip Platform for Cyber-Physical System Analysis., , , , , and . IEEE Embed. Syst. Lett., 6 (1): 4-7 (2014)Hardware architectural support for control systems and sensor processing., , , , , and . ACM Trans. Embed. Comput. Syst., 13 (2): 16:1-16:25 (2013)