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A self-tuning DVS processor using delay-error detection and correction.

, , , , , , , and . IEEE J. Solid State Circuits, 41 (4): 792-804 (2006)

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An ECL RISC microprocessor designed for two level cache., , and . Compcon, page 228-231. IEEE Computer Society, (1990)M-N scatter plots technique for evaluating varying-size clusters and setting the parameters of Bi-CoPaM and Uncles methods., , , and . ICASSP, page 6726-6730. IEEE, (2014)Splitting-while-merging framework for clustering high-dimension data with component-wise expectation conditional maximisation., , , and . ICASSP, page 2932-2936. IEEE, (2014)Individuum und Kollektiv: Jünger und Brecht zu Ausgang der Weimarer Republik. Orbis Litterarum, (1986)HpMC: An Energy-aware Management System of Multi-level Memory Architectures., , , , , , and . MEMSYS, page 167-178. ACM, (2015)Integrating NAND flash devices onto servers., , and . Commun. ACM, 52 (4): 98-103 (2009)On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology., , and . DSD, page 570-578. IEEE Computer Society, (2007)System design for a low cost PA-RISC desktop workstation., , , , , , and . Compcon, page 208-213. IEEE Computer Society, (1991)Using non-volatile memory to save energy in servers., , and . DATE, page 743-748. IEEE, (2009)On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology., , and . Microprocess. Microsystems, 32 (5-6): 244-253 (2008)