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Disambiguation of "López, Juan A."

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Fast and accurate computation of the roundoff noise of linear time-invariant systems.

, , , and . IET Circuits Devices Syst., 2 (4): 393-408 (2008)

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Juan López-Pila

Juan López Gejo

Juan Antonio Cuéllar López

Juan Manuel Salgado López

Juan Miguel Rodríguez López

 

Other publications of authors with the same name

Bit-Width Selection for Data-Path Implementations., , and . ISSS, page 114-121. ACM / IEEE Computer Society, (1999)Fast characterization of the noise bounds derived from coefficient and signal quantization., , , and . ISCAS (4), page 309-312. IEEE, (2003)Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs., , , , and . Int. J. Reconfigurable Comput., (2009)Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes., , , , , and . J. Syst. Archit., 60 (7): 579-591 (2014)Improved Interval-Based Characterization of Fixed-Point LTI Systems With Feedback Loops., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (11): 1923-1933 (2007)Fast and accurate computation of the roundoff noise of linear time-invariant systems., , , and . IET Circuits Devices Syst., 2 (4): 393-408 (2008)SQNR Estimation of Fixed-Point DSP Algorithms., , , and . EURASIP J. Adv. Signal Process., (2010)Any-Radix Efficient Fully-Parallel Implementation of the Fast Fourier Transform on FPGAs., and . DCIS, page 1-6. IEEE, (2023)High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs., , , and . FPL, page 1-4. IEEE, (2006)High-speed systolic array for gene matching., , , , and . FPGA, page 248. ACM, (2004)