( en | de | ru )

 

Disambiguation of "Martins, Rui Paulo"

Author of the publication

copydeleteadd this publication to your clipboard
An I/Q-multiplexed and OTA-shared CMOS pipelined ADC with an A-DQS S/H front-end for two-step-channel-select low-IF receiver.

, , , , , , , and . ISCAS (1), page 1068-1071. IEEE, (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Paulo Martins Engel

Paulo Ney Aguiar Martins

Milan Paulovic

Manuel António Paulo

Hartwig Paulo

 

Other publications of authors with the same name

Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (3): 1203-1207 (2016)Passive Noise Shaping in SAR ADC With Improved Efficiency., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (2): 416-420 (2018)A 0.45 V 147-375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (4): 1307-1319 (2017)Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (2): 481-485 (2019)A 52.5-dB 2× Time-Interleaved 2.8-GS/s SAR ADC With 5-bit/Cycle Time-Domain Quantization and a Compact Signal DAC., , , , and . IEEE J. Solid State Circuits, 58 (12): 3586-3597 (December 2023)A Single-Stage Dual-Output Regulating Rectifier With Hysteretic Current-Wave Modulation., , , and . IEEE J. Solid State Circuits, 56 (9): 2770-2780 (2021)A 0.35-V 5, 200-μm2 2.1-MHz Temperature-Resilient Relaxation Oscillator With 667 fJ/Cycle Energy Efficiency Using an Asymmetric Swing-Boosted RC Network and a Dual-Path Comparator., , and . IEEE J. Solid State Circuits, 56 (9): 2701-2710 (2021)A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC With Gain and Offset Calibrations., , , , , , and . IEEE J. Solid State Circuits, 57 (3): 745-756 (2022)A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 45 (6): 1111-1121 (2010)A 550- $\mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $\Sigma\Delta$ ADC With 256 Clock Cycles in 65-nm CMOS., , , , and . IEEE J. Solid State Circuits, 54 (4): 1161-1172 (2019)