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Ultra-low power challenges for the next generation ASIC.. ISLPED, page 365-366. ACM, (2012)High-performance, low-power design techniques for dynamic to static logic interface., , and . ISLPED, page 12-17. ACM, (1997)Solutions for logic and processor core design at the 45nm technology node & and below., , , and . ICECS, page 923-926. IEEE, (2007)DSP for the Third Generation Wireless Communications., , and . ICCD, page 516-520. IEEE Computer Society, (1999)A design platform for 90-nm leakage reduction techniques., , , , , , , , , and 4 other author(s). DAC, page 549-550. ACM, (2005)Entering the hot zone - can you handle the heat and be cool?, , , , , and . DAC, page 174-175. ACM, (2006)Short-circuit power driven gate sizing technique for reducing power dissipation., and . IEEE Trans. Very Large Scale Integr. Syst., 3 (3): 450-455 (1995)Hybrid dual-threshold design techniques for high-performance processors with low-power features., , , and . ISLPED, page 307-311. ACM, (1997)Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference., , , , and . IEEE J. Solid State Circuits, 48 (1): 3-7 (2013)Low-power design techniques for high-performance CMOS adders., , and . IEEE Trans. Very Large Scale Integr. Syst., 3 (2): 327-333 (1995)