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Recent Advances and New Avenues in Hardware-Level Reliability Support., , , and . IEEE Micro, 25 (6): 18-29 (2005)Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications., , , , , , , , and . IEEE Micro, 42 (6): 116-124 (2022)Bug localization techniques for effective post-silicon validation., , , and . ASP-DAC, page 291. IEEE, (2012)The resilience wall: Cross-layer solution strategies., , , , , , , , , and 3 other author(s). VLSI-DAT, page 1-11. IEEE, (2014)A Design Diversity Metric and Analysis of Redundant Systems., , and . IEEE Trans. Computers, 51 (5): 498-510 (2002)Transforming nanodevices into nanosystems: The N3XT 1, 000X.. LATS, page 6. IEEE, (2016)Hot Chips 28., and . IEEE Micro, 37 (2): 5-6 (2017)System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits., , , , , and . JETC, 10 (4): 33:1-33:19 (2014)Cross-layer resilience challenges: Metrics and optimization., , and . DATE, page 1029-1034. IEEE Computer Society, (2010)Subhasish Mitra, Norbert Seifert, Ming Zhang, Quan Shi, Kee Sup Kim., , , , and . Computer, 38 (2): 43-52 (2005)