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Disambiguation of "Paul, Bipul Chandra"

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ROM based logic (RBL) design: High-performance and low-power adders.

, , and . ISCAS, page 796-799. IEEE, (2008)

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Bipul Sen

Chandra Paul Leo

Umananda Chandra

Harish Chandra

Sunil Chandra

 

Other publications of authors with the same name

ROM based logic (RBL) design: High-performance and low-power adders., , and . ISCAS, page 796-799. IEEE, (2008)An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (12): 2765-2774 (2006)Device optimization for ultra-low power digital sub-threshold operation., , and . ISLPED, page 96-101. ACM, (2004)Novel sizing algorithm for yield improvement under process variation in nanometer technology., , and . DAC, page 454-459. ACM, (2004)Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis., and . ITC, page 384-390. IEEE Computer Society, (2002)Statistical Timing Analysis using Levelized Covariance Propagation., , and . DATE, page 764-769. IEEE Computer Society, (2005)Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies., , , and . DATE, page 856-861. European Design and Automation Association, Leuven, Belgium, (2006)Dynamic Noise Analysis with Capacitive and Inductive Coupling., , and . ASP-DAC/VLSI Design, page 65-70. IEEE Computer Society, (2002)Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits., , and . ITC, page 1269-1275. IEEE Computer Society, (2004)Design Verification and Robust Design Technique for Cross-Talk Faults., , , and . Asian Test Symposium, page 449-. IEEE Computer Society, (2001)