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Reducing Performance Impact of DRAM Refresh by Parallelizing Refreshes with Accesses., , , , , , and . CoRR, (2016)Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance., , , , , , , and . IEEE J. Solid State Circuits, 44 (1): 49-63 (2009)Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops., , , , , , , , , and 1 other author(s). IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (3): 208-217 (2011)The efficacy of error mitigation techniques for DRAM retention failures: a comparative experimental study., , , , , and . SIGMETRICS, page 519-532. ACM, (2014)Path confidence based lookahead prefetching., , , , , and . MICRO, page 60:1-60:12. IEEE Computer Society, (2016)Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors., , , and . HPCA, page 129-140. IEEE Computer Society, (2003)Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers., , , , , , , , and . HPCA, page 626-637. IEEE Computer Society, (2014)Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors., , , , , , , , and . ISCA, page 361-372. IEEE Computer Society, (2014)Energy-efficient cache design using variable-strength error-correcting codes., , , , , and . ISCA, page 461-472. ACM, (2011)Circuit techniques for dynamic variation tolerance., , , , , , and . DAC, page 4-7. ACM, (2009)