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Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms.

, , and . CASES, page 145-149. ACM, (2007)

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A tightly-coupled multi-core cluster with shared-memory HW accelerators., , , , , and . ICSAMOS, page 96-103. IEEE, (2012)On the Cost of Freedom From Interference in Heterogeneous SoCs., , and . SCOPES, page 31-34. ACM, (2018)Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution., , , , , and . ACM Great Lakes Symposium on VLSI, page 9-14. ACM, (2015)Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators., , , , , and . IEEE Trans. Computers, 64 (8): 2132-2144 (2015)Mixed-data-model heterogeneous compilation and OpenMP offloading., , , , , , and . CC, page 119-131. ACM, (2020)A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment., , , and . DSD, page 9-17. IEEE, (2021)OpenMP Support for NBTI-Induced Aging Tolerance in MPSoCs., , and . SSS, volume 5873 of Lecture Notes in Computer Science, page 547-562. Springer, (2009)Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs., , , , , , and . DATE, page 491-496. IEEE, (2012)Analysis of Power Management Strategies for a Large-Scale SoC Platform in 65nm Technology., , , and . DSD, page 259-266. IEEE Computer Society, (2008)A Software Stack for Next-Generation Automotive Systems on Many-Core Heterogeneous Platforms., , , , , and . DSD, page 55-59. IEEE Computer Society, (2016)