Author of the publication

A 5-GHz 108-Mb/s 2 $\times$2 MIMO Transceiver RFIC With Fully Integrated 20.5-dBm $P_1dB$ Power Amplifiers in 90-nm CMOS.

, , , , , , , , , , , and . IEEE J. Solid State Circuits, 41 (12): 2746-2756 (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A 5-GHz 108-Mb/s 2 $\times$2 MIMO Transceiver RFIC With Fully Integrated 20.5-dBm $P_1dB$ Power Amplifiers in 90-nm CMOS., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 41 (12): 2746-2756 (2006)A 90-nm MOS-only 3-11GHz transmitter for UWB., , , and . CICC, page 165-168. IEEE, (2005)A 5 GHz class-AB power amplifier in 90 nm CMOS with digitally-assisted AM-PM correction., , , , , , , and . CICC, page 813-816. IEEE, (2005)Dynamic Control of Spring-driven Mechanisms., and . IBM J. Res. Dev., 16 (3): 222-230 (1972)A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process., , , , , , , and . IEEE J. Solid State Circuits, 41 (8): 1757-1763 (2006)A 5GHz 108Mb/s 2x2 MIMO Transceiver with Fully Integrated +16dBm PAs in 90nm CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 1420-1429. IEEE, (2006)8 GHz, 20mW, fast locking, fractional-N frequency synthesizer with optimized 3rd order, 3/5-bit IIR and 3rd order 3-bit-FIR noise shapers in 90nm CMOS., , , and . CICC, page 625-628. IEEE, (2004)