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Disambiguation of "Park, Sanghune"

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Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface.

, , , , , and . ISOCC, page 140-141. IEEE, (2018)

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Sungjune Park

Rosemary Park

Jinhyung Park

Kwan Park

Shinja Park

 

Other publications of authors with the same name

22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique., , , , , , , , , and 6 other author(s). ISSCC, page 338-340. IEEE, (2020)An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme., , , , , , , , , and 8 other author(s). VLSI Circuits, page 96-. IEEE, (2019)A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection., , , , , , , , , and 8 other author(s). ISSCC, page 406-407. IEEE, (2023)Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface., , , , , and . ISOCC, page 140-141. IEEE, (2018)A Low-Power Post-LPDDR4 Interface Using AC Termination at RX and an Active Inductor at TX., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (6): 789-793 (2018)A 690mV 4.4Gbps/pin all-digital LPDDR4 PHY in 10nm FinFET technology., , , , , , , , , and 1 other author(s). ESSCIRC, page 461-464. IEEE, (2016)23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller., , , , , , , , , and 7 other author(s). ISSCC, page 398-399. IEEE, (2017)A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 59 (1): 231-242 (January 2024)A 16GHz 33fs rms Integrated Jitter FLL-less Gear Shifting Reference Sampling PLL., , , , , , and . CICC, page 1-2. IEEE, (2023)A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques., , , , , , , , , and 6 other author(s). ISSCC, page 114-115. IEEE, (2023)