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Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface.

K. Chae, B. Koo, J. Oh, S. Park, J. Shin, и J. Park. ISOCC, стр. 140-141. IEEE, (2018)

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Dong-Shin Shin

Jeonghun Shin

Kirche als Weltforum: zum Dialogverständnis in kirchlichen Dokumenten seit dem Zweiten Vatikanischen KonzilJ. Shin. Uni München, (2009)

Hwa-Ja Shin

Jung-Hyu Shin

Hyeseon Shin

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A 0.65V 1316µm2Fully Synthesizable Digital Temperature Sensor Using Wire Metal Achieving O.16nJ.%2-Accuracy FoM in 5nm FinFET CMOS.J. Park, J. Kim, K. Kim, J. Yang, M. Choi, и J. Shin. ISSCC, стр. 220-222. IEEE, (2022)At-speed logic BIST using a frozen clock testing strategy.J. Shin, X. Yu, E. Rudnick, и M. Abramovici. ITC, стр. 64-71. IEEE Computer Society, (2001)Compact and Broadband ESD Protection I/O Pad Using Pad-Stacked Inductor.J. Jeong, H. Kim, J. Park, J. Shin, и J. Jeong. IEEE Access, (2023)A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization.S. Choi, H. Son, J. Shin, S. Lee, B. Kim, H. Park, и J. Sim. IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (2): 276-287 (2016)6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier.B. Yoo, D. Lim, H. Pang, J. Lee, S. Baek, N. Kim, D. Choi, Y. Choi, H. Yang, T. Yoon и 9 other автор(ы). ISSCC, стр. 122-124. IEEE, (2020)22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique.S. Lee, K. Seong, J. Shin, H. Kim, J. Jeong, S. Yi, J. Kim, E. Kim, S. Jung, S. Hwang и 6 other автор(ы). ISSCC, стр. 338-340. IEEE, (2020)An Automotive ASIL-D Safety Mechanism in ADC and DAC for Communication Application.K. Lee, J. Park, Y. Park, B. Koo, S. Do, W. Lim, S. Lee, H. Shin, E. Oh, Y. Cho и 2 other автор(ы). VLSI Technology and Circuits, стр. 142-143. IEEE, (2022)A Low-Jitter Added SSCG with Seamless Phase Selection and Fast AFC for 3rd Generation Serial-ATA.J. Shin, I. Seo, J. Kim, S. Yang, C. Kim, J. Park, H. Kim, M. Kwak, и G. Hong. CICC, стр. 409-412. IEEE, (2006)A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection.K. Chae, J. Song, Y. Choi, J. Park, B. Koo, J. Oh, S. Yi, W. Lee, D. Kim, K. Kang и 7 other автор(ы). IEEE J. Solid State Circuits, 59 (1): 231-242 (января 2024)A 16GHz 33fs rms Integrated Jitter FLL-less Gear Shifting Reference Sampling PLL.J. Lee, Y. Jo, W. Yu, W. Kim, M. Choi, S. Park, и J. Shin. CICC, стр. 1-2. IEEE, (2023)

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