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Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch.

, , , и . IEICE Trans. Inf. Syst., 89-D (3): 1165-1172 (2006)

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Esther Fujiwara

Hideo Baba

Hideo Ohashi

Hideo Andreas Baba

Hideo Ikezawa-Hanada

 

Другие публикации лиц с тем же именем

The Complexity of Fault Detection Problems for Combinational Logic Circuits., и . IEEE Trans. Computers, 31 (6): 555-560 (1982)Brief Announcement: Acceleration by Contention for Shared Memory Mutual Exclusion Algorithms., , и . DISC, том 5805 из Lecture Notes in Computer Science, стр. 172-173. Springer, (2009)Optimal Wait-Free Clock Synchronisation Protocol on a Shared-Memory Multi-processor System., , , и . WDAG, том 1320 из Lecture Notes in Computer Science, стр. 290-304. Springer, (1997)Effect of BIST Pretest on IC Defect Level., , и . IEICE Trans. Inf. Syst., 89-D (10): 2626-2636 (2006)A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips., , и . IEICE Trans. Inf. Syst., 89-D (4): 1490-1497 (2006)Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints., , , и . IEICE Trans. Inf. Syst., 91-D (3): 807-814 (2008)A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification., , и . IEICE Trans. Inf. Syst., 93-D (7): 1857-1865 (2010)Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents., и . IEICE Trans. Inf. Syst., 100-D (9): 2232-2236 (2017)Strongly Secure Scan Design Using Generalized Feed Forward Shift Registers., и . IEICE Trans. Inf. Syst., 98-D (10): 1852-1855 (2015)Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability., , , и . IEICE Trans. Inf. Syst., 90-D (1): 296-305 (2007)