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Reachability analysis in RTL circuits using k-induction bounded model checking., and . HLDVT, page 9-16. IEEE Computer Society, (2017)Converting Natural Language Text to ROS-Compatible Instruction Base., and . AIVR, page 219-226. IEEE Computer Society, (2018)Guiding RTL Test Generation Using Relevant Potential Invariants., and . ICCD, page 449-455. IEEE Computer Society, (2018)RTL Test Generation on Multi-core and Many-Core Architectures., and . VLSID, page 100-105. IEEE, (2019)Information-theoretic and statistical methods of failure log selection for improved diagnosis., , , and . ITC, page 1-10. IEEE, (2015)Dynamic state traversal for sequential circuit test generation., , and . ACM Trans. Design Autom. Electr. Syst., 5 (3): 548-565 (2000)Effective safety property checking using simulation-based sequential ATPG., , and . DAC, page 813-818. ACM, (2002)Compiler-directed dynamic voltage/frequency scheduling for energy reduction in mircoprocessors., , and . ISLPED, page 275-278. ACM, (2001)Fast, flexible, cycle-accurate energy estimation., and . ISLPED, page 141-146. ACM, (2001)Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains., , , , , , , , , and 2 other author(s). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (3): 455-463 (2011)