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The Cydram 5 Stride-Insensitive Memory System.

, , and . ICPP (1), page 242-246. Pennsylvania State University Press, (1989)

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Compilers for Instruction-Level Parallelism., , , , , and . Computer, 30 (12): 63-69 (1997)Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks., , , , , and . MICRO, page 58-67. ACM/IEEE Computer Society, (1996)Configurable optical interconnects for scalable datacenters., , , , and . OFC/NFOEC, page 1-3. IEEE, (2013)Parallelization of WHILE loops on pipelined architectures., , and . J. Supercomput., 5 (2-3): 119-136 (1991)Cydra 5.. Encyclopedia of Parallel Computing, Springer, (2011)Global Predicate Analysis and Its Application to Register Allocation., , , and . MICRO, page 114-125. ACM/IEEE Computer Society, (1996)Spill-free parallel scheduling of basic blocks., and . MICRO, page 119-124. ACM / IEEE Computer Society, (1995)Code generation schema for modulo scheduled loops., , and . MICRO, page 158-169. ACM / IEEE Computer Society, (1992)A microprogramming language for the B-1726., , and . MICRO, page 21-29. ACM, (1973)Bitwidth cognizant architecture synthesis of custom hardwareaccelerators., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (11): 1355-1371 (2001)