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A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.

J. Oh, S. Lee, M. Kang, M. Ziegler, J. Silberman, A. Agrawal, S. Venkataramani, B. Fleischer, M. Guillorn, J. Choi, W. Wang, S. Mueller, S. Ben-Yehuda, J. Bonanno, N. Cao, R. Casatuta, C. Chen, M. Cohen, O. Erez, T. Fox, G. Gristede, H. Haynie, V. Ivanov, S. Koswatta, S. Lo, M. Lutz, G. Maier, A. Mesh, Y. Nustov, S. Rider, M. Schaal, M. Scheuermann, X. Sun, N. Wang, F. Yee, C. Zhou, V. Shah, B. Curran, V. Srinivasan, P. Lu, S. Shukla, K. Gopalakrishnan, и L. Chang. VLSI Circuits, стр. 1-2. IEEE, (2020)

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George Mertzios

Combinatorial optimization and recognition of graph classes with applications to related modelsG. Mertzios. TU Aachen, (2009)

George Marinescu

George Couplanad

Andrew George

George Bandlamudi

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A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR).M. Vratonjic, M. Ziegler, G. Gristede, V. Zyuban, T. Mitchell, E. Cho, C. Visweswariah, и V. Oklobdzija. PATMOS, том 5953 из Lecture Notes in Computer Science, стр. 307-316. Springer, (2009)A comparison of dual-rail pass transistor logic families in 1.5V, 0.18µm CMOS technology for low power applications.G. Gristede, и W. Hwang. ACM Great Lakes Symposium on VLSI, стр. 101-106. ACM, (2000)Across the Stack Opportunities for Deep Learning Acceleration.V. Srinivasan, B. Fleischer, S. Shukla, M. Ziegler, J. Silberman, J. Oh, J. Choi, S. Mueller, A. Agrawal, T. Babinsky и 21 other автор(ы). ISLPED, стр. 35:1-35:2. ACM, (2018)Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design.W. Chen, W. Hwang, P. Kudva, G. Gristede, S. Kosonocky, и R. Joshi. ISLPED, стр. 263-266. ACM, (2001)A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.B. Fleischer, S. Shukla, M. Ziegler, J. Silberman, J. Oh, V. Srinivasan, J. Choi, S. Mueller, A. Agrawal, T. Babinsky и 21 other автор(ы). VLSI Circuits, стр. 35-36. IEEE, (2018)A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.J. Oh, S. Lee, M. Kang, M. Ziegler, J. Silberman, A. Agrawal, S. Venkataramani, B. Fleischer, M. Guillorn, J. Choi и 33 other автор(ы). VLSI Circuits, стр. 1-2. IEEE, (2020)A Scalable Black-Box Optimization System for Auto-Tuning VLSI Synthesis Programs.M. Ziegler, H. Liu, G. Gristede, B. Owens, R. Nigaglioni, и L. Carloni. RES4ANT@DATE, том 1643 из CEUR Workshop Proceedings, стр. 8-12. CEUR-WS.org, (2016)Characterization of logic circuit techniques for high leakage CMOS technologies.P. Chin, C. Zukowski, G. Gristede, и S. Kosonocky. ACM Great Lakes Symposium on VLSI, стр. 230-235. ACM, (2004)The opportunity cost of low power design: a case study in circuit tuning.M. Ziegler, V. Zyuban, G. Gristede, M. Vratonjic, и J. Friedrich. ISLPED, стр. 133-138. ACM, (2009)Measuring Error Propagation in Waveform Relaxation Algorithms.C. Zukowski, G. Gristede, и A. Ruehli. ICCAD, стр. 170-173. IEEE Computer Society, (1990)

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Please choose a person to relate this publication to

George Mertzios

George Marinescu

George Couplanad

Andrew George

George Bandlamudi

Другие публикации лиц с тем же именем

Disambiguation