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A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.

J. Oh, S. Lee, M. Kang, M. Ziegler, J. Silberman, A. Agrawal, S. Venkataramani, B. Fleischer, M. Guillorn, J. Choi, W. Wang, S. Mueller, S. Ben-Yehuda, J. Bonanno, N. Cao, R. Casatuta, C. Chen, M. Cohen, O. Erez, T. Fox, G. Gristede, H. Haynie, V. Ivanov, S. Koswatta, S. Lo, M. Lutz, G. Maier, A. Mesh, Y. Nustov, S. Rider, M. Schaal, M. Scheuermann, X. Sun, N. Wang, F. Yee, C. Zhou, V. Shah, B. Curran, V. Srinivasan, P. Lu, S. Shukla, K. Gopalakrishnan, and L. Chang. VLSI Circuits, page 1-2. IEEE, (2020)

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Fei Fei

Dennis Pong

Lu Lu

Kin-Pong Chik

Wen-berng Pong

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A Semi-Custom Design Flow in High-Performance Microprocessor Design.G. Northrop, and P. Lu. DAC, page 426-431. ACM, (2001)A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors.P. Lu, N. Cao, L. Sigal, P. Woltgens, R. Robertazzi, and D. Heidel. ISLPED, page 85-88. ACM, (2006)Across the Stack Opportunities for Deep Learning Acceleration.V. Srinivasan, B. Fleischer, S. Shukla, M. Ziegler, J. Silberman, J. Oh, J. Choi, S. Mueller, A. Agrawal, T. Babinsky and 21 other author(s). ISLPED, page 35:1-35:2. ACM, (2018)A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.B. Fleischer, S. Shukla, M. Ziegler, J. Silberman, J. Oh, V. Srinivasan, J. Choi, S. Mueller, A. Agrawal, T. Babinsky and 21 other author(s). VLSI Circuits, page 35-36. IEEE, (2018)Floating body effects in partially-depleted SOI CMOS circuits.P. Lu, J. Ji, C. Chuang, L. Wagner, C. Hsieh, J. Kuang, ouis Lu-Chen Hsu, M. Jr., S. Chu, and C. Anderson. ISLPED, page 139-144. IEEE, (1996)A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling.A. Agrawal, S. Lee, J. Silberman, M. Ziegler, M. Kang, S. Venkataramani, N. Cao, B. Fleischer, M. Guillorn, M. Cohen and 34 other author(s). ISSCC, page 144-146. IEEE, (2021)On-chip circuit to monitor long-term NBTI and PBTI degradation.K. Jenkins, and P. Lu. Microelectron. Reliab., 53 (9-11): 1252-1256 (2013)Synthesis design strategies for energy-efficient microprocessors.C. Zhou, Y. Lin, P. Lu, B. Fleischer, D. Frank, and L. Chang. ICCD, page 103-108. IEEE Computer Society, (2016)A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.J. Oh, S. Lee, M. Kang, M. Ziegler, J. Silberman, A. Agrawal, S. Venkataramani, B. Fleischer, M. Guillorn, J. Choi and 33 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)RaPiD: AI Accelerator for Ultra-low Precision Training and Inference.S. Venkataramani, V. Srinivasan, W. Wang, S. Sen, J. Zhang, A. Agrawal, M. Kar, S. Jain, A. Mannari, H. Tran and 44 other author(s). ISCA, page 153-166. IEEE, (2021)

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Disambiguation of "Lu, Pong-Fei"

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A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.

Please choose a person to relate this publication to

Fei Fei

Dennis Pong

Lu Lu

Kin-Pong Chik

Wen-berng Pong

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lu, Pong-Fei"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.

Please choose a person to relate this publication to

Fei Fei

Dennis Pong

Lu Lu

Kin-Pong Chik

Wen-berng Pong

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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MSOffice XML

A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.