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A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR).

M. Vratonjic, M. Ziegler, G. Gristede, V. Zyuban, T. Mitchell, E. Cho, C. Visweswariah, and V. Oklobdzija. PATMOS, volume 5953 of Lecture Notes in Computer Science, page 307-316. Springer, (2009)

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V Saile

V Geoffroy

V Ustinov

V Adams

V Fendrich

Other publications of authors with the same name

Inherently Lower-Power High-Performance Superscalar Architectures.V. Zyuban, and P. Kogge. IEEE Trans. Computers, 50 (3): 268-285 (2001)Unified architecture level energy-efficiency metric.V. Zyuban. ACM Great Lakes Symposium on VLSI, page 24-29. ACM, (2002)Design methodology for semi custom processor cores.V. Zyuban, S. Asaad, T. Fox, A. Haen, D. Littrell, and J. Moreno. ACM Great Lakes Symposium on VLSI, page 448-452. ACM, (2004)A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime.J. Shin, V. Zyuban, P. Bose, and T. Pinkston. ISCA, page 353-362. IEEE Computer Society, (2008)Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis.N. Dhanwada, D. Hathaway, V. Zyuban, P. Peng, K. Moody, W. Dungan, A. Joseph, R. Rao, and C. Gonzalez. ICCAD, page 458-465. IEEE, (2013)The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.E. Fluhr, S. Baumgartner, D. Boerstler, J. Bulzacchelli, T. Diemoz, D. Dreps, G. English, J. Friedrich, A. Gattiker, T. Gloekler and 20 other author(s). IEEE J. Solid State Circuits, 50 (1): 10-23 (2015)Optimizing pipelines for power and performance.V. Srinivasan, D. Brooks, M. Gschwind, P. Bose, V. Zyuban, P. Strenski, and P. Emma. MICRO, page 333-344. ACM/IEEE Computer Society, (2002)IBM POWER8 circuit design and energy optimization.V. Zyuban, J. Friedrich, D. Dreps, J. Pille, D. Plass, P. Restle, Z. Deniz, M. Ziegler, S. Chu, M. Islam and 13 other author(s). IBM J. Res. Dev., (2015)Optimization of scannable latches for low energy.V. Zyuban. IEEE Trans. Very Large Scale Integr. Syst., 11 (5): 778-788 (2003)Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels.V. Zyuban, and P. Strenski. ISLPED, page 166-171. ACM, (2002)

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Disambiguation of "Zyuban, Victor V."

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A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR).

Please choose a person to relate this publication to

V Saile

V Geoffroy

V Ustinov

V Adams

V Fendrich

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Zyuban, Victor V."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR).

Please choose a person to relate this publication to

V Saile

V Geoffroy

V Ustinov

V Adams

V Fendrich

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR).