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Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques., , , , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (6): 2249-2262 (2022)Interactive Analog Layout Editing With Instant Placement and Routing Legalization., , , , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (3): 698-711 (марта 2023)A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- ΔΣ M Structure., , , , , , , , и . IEEE J. Solid State Circuits, 55 (3): 666-679 (2020)A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS., , , , , , и . IEEE J. Solid State Circuits, 56 (2): 476-487 (2021)An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter., , , , , , , , , и 1 other автор(ы). IEEE J. Solid State Circuits, 55 (11): 3064-3075 (2020)An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier., , , , , , , и . IEEE J. Solid State Circuits, 55 (4): 1011-1022 (2020)A 77μW 115dB-Dynamic-Range 586fA-Sensitivity Current-Domain Continuous-Time Zoom ADC with Pulse-Width-Modulated Resistor DAC and Background Offset Compensation Scheme., , , , , , , и . CICC, стр. 1-2. IEEE, (2022)A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based Correlated Level Shifting., , , , , , , , , и . ISSCC, стр. 346-347. IEEE, (2023)9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 174-176. IEEE, (2024)WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout., , , , , , и . DAC, стр. 66. ACM, (2019)