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Post-Layout Simulation Driven Analog Circuit Sizing.

X. Gao, H. Zhang, S. Ye, M. Liu, D. Pan, L. Shen, R. Wang, Y. Lin, and R. Huang. CoRR, (2023)

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Siyuan Ma

Ying Ye

Ye Chen

Ye Hu

Fei Ye

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A 12.5-ppm/°C 1.086-nW/kHz Relaxation Oscillator with Clock-Gated Discrete-Time Comparator in 22nm CMOS Technology.X. Xu, L. Shen, S. Ye, J. Wu, Z. Chen, J. Gao, J. Cui, Y. Zhang, R. Huang, and L. Ye. ESSCIRC, page 121-124. IEEE, (2023)Heterogeneous graphlets-guided network embedding via eulerian-trail-based representation.G. Mei, S. Ye, S. Liu, L. Pan, and Q. Li. Inf. Sci., (April 2023)A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based Correlated Level Shifting.J. Gao, L. Shen, H. Li, S. Ye, J. Li, X. Xu, J. Cui, Y. Gao, R. Huang, and L. Ye. ISSCC, page 346-347. IEEE, (2023)9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique.Z. Chen, L. Shen, S. Ye, J. Gao, J. Li, J. Cui, X. Xu, Y. Luan, H. Zhang, L. Ye and 1 other author(s). ISSCC, page 174-176. IEEE, (2024)How the four-nodes motifs work in heterogeneous node representation?S. Ye, Q. Li, G. Mei, S. Liu, and L. Pan. World Wide Web (WWW), 26 (4): 1707-1729 (July 2023)Post-Layout Simulation Driven Analog Circuit Sizing.X. Gao, H. Zhang, S. Ye, M. Liu, D. Pan, L. Shen, R. Wang, Y. Lin, and R. Huang. CoRR, (2023)A 32-ppm/°C 0.9-nW/kHz Relaxation Oscillator with Event-Driven Architecture and Charge Reuse Technique.X. Xu, S. Ye, J. Gao, Y. Zhang, L. Shen, and L. Ye. ISCAS, page 1973-1977. IEEE, (2022)A Readout Circuit with Current-Compensation-Based Extended-Counting ADC for 1024×768 Diode Uncooled Infrared Imagers.S. Yu, X. Shi, Y. Zhang, G. Chen, S. Ye, W. Lu, and Z. Chen. ISCAS, page 1-5. IEEE, (2021)3.10 A 0.69/0.58-PEF 1.6nW/24nW Capacitively Coupled Chopper Instrumentation Amplifier with an Input-Boosted First Stage in 22nm/180nm CMOS.X. Xu, S. Ye, Y. Luan, J. Gao, J. Li, J. Cui, H. Zhang, R. Huang, L. Shen, and L. Ye. ISSCC, page 72-74. IEEE, (2024)9.1 A 2mW 70.7dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level Shifting.S. Ye, L. Shen, J. Gao, J. Li, Z. Chen, X. Xu, J. Cui, H. Zhang, X. Zhang, L. Ye and 1 other author(s). ISSCC, page 168-170. IEEE, (2024)

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Disambiguation of "Ye, Siyuan"

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Post-Layout Simulation Driven Analog Circuit Sizing.

Please choose a person to relate this publication to

Siyuan Ma

Ying Ye

Ye Chen

Ye Hu

Fei Ye

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Ye, Siyuan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Post-Layout Simulation Driven Analog Circuit Sizing.

Please choose a person to relate this publication to

Siyuan Ma

Ying Ye

Ye Chen

Ye Hu

Fei Ye

Other publications of authors with the same name

Disambiguation

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URL
DOI
BibTeX
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APA
Chicago
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Post-Layout Simulation Driven Analog Circuit Sizing.