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Disambiguation of "Li, Zhaofang"

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An Area-Efficient Accelerator for Non-Maximum Suppression.

, , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (6): 2251-2255 (June 2023)

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Li Li

Li Li

Li Li

Li Li

Li Li

 

Other publications of authors with the same name

An Area-Efficient Accelerator for Non-Maximum Suppression., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (6): 2251-2255 (June 2023)A 1.93TOPS/W Deep Learning Processor with a Reconfigurable Processing Element Array Based on SRAM Access Optimization., , , , and . APCCAS, page 15-19. IEEE, (2022)LG-LSQ: Learned Gradient Linear Symmetric Quantization., , , , , and . CoRR, (2022)MARSv2: Multicore and Programmable Reconstruction Architecture SRAM CIM-Based Accelerator with Lightweight Network., , , , , and . AICAS, page 383-386. IEEE, (2022)A Two-stage Training Framework for Hardware Constraints of Computing-in-Memory Architecture., , , , , and . APCCAS, page 30-34. IEEE, (2022)MARS: Multimacro Architecture SRAM CIM-Based Accelerator With Co-Designed Compressed Neural Networks., , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (5): 1550-1562 (2022)A 40nm area-efficient Effective-bit-combination-based DNN accelerator with the reconfigurable multiplier., , , , and . AICAS, page 1-5. IEEE, (2023)LG-LSQ: Learned Gradient Linear Symmetric Quantization for Low-Precision Integer Hardware., , , , , , , and . AICAS, page 1-5. IEEE, (2023)A 62.45 TOPS/W Spike-Based Convolution Neural Network Accelerator with Spatiotemporal Parallel Data Flow and Sparsity Mechanism., , , , and . AICAS, page 182-185. IEEE, (2022)A 104.76-TOPS/W, Spike-Based Convolutional Neural Network Accelerator with Reduced On-Chip Memory Data Flow and Operation Unit Skipping., , , , , and . APCCAS, page 41-45. IEEE, (2022)