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A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM.

X. Shen, Z. Zhang, G. Li, Y. Chen, N. Qi, J. Liu, N. Wu, and L. Liu. ESSCIRC, page 257-260. IEEE, (2023)

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Li Li

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A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O.S. Chen, M. You, Y. Yang, Y. Jin, Z. Lin, Y. Li, L. Li, G. Li, Y. Xie, Z. Zhang and 11 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 70 (11): 4271-4282 (November 2023)A 400-Gb/s 64-QAM Optical Receiver with Monolithically Integrated TIA and Balanced-PD in 45-nm SOI CMOS.Y. Xiong, Y. Yang, Q. Ma, Y. Ren, L. Li, G. Li, J. Liu, Y. Li, B. Wang, N. Qi and 1 other author(s). ICTA, page 186-187. IEEE, (2023)A Fast-Transient Capacitor-Less Low-Dropout Regulator for Wideband Optical Transceivers.H. Liu, G. Li, J. Liu, N. Wu, L. Liu, Y. Li, and N. Qi. ICTA, page 257-258. IEEE, (2021)A $4 112-Gb/s$ PAM-4 Silicon-Photonic Transceiver Front-End for Linear-Drive Co-Packaged Optics.H. Liu, N. Qi, D. Lu, Z. Dong, Z. Zhang, J. He, G. Li, L. Li, Y. Liu, Z. Dang and 6 other author(s). A-SSCC, page 1-3. IEEE, (2023)A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR.Q. Liao, Y. Zhang, S. Ma, L. Wang, L. Li, G. Li, Z. Zhang, J. Liu, N. Wu, L. Liu and 3 other author(s). IEEE J. Solid State Circuits, 57 (3): 767-780 (2022)A 4×25Gb/s De-Serializer with Baud-Rate Sampling CDR and Standing-Wave Clock Distribution for NIC Optical Interconnects.M. You, M. Chen, Y. Li, G. Li, J. Liu, Y. Chen, Y. Li, and N. Qi. ICTA, page 253-254. IEEE, (2021)A 56Gb/s De-serializer with PAM-4 CDR for Chiplet Optical-I/O.Y. Yang, M. Zhong, Q. Ma, Z. Lin, L. Li, G. Li, L. Liu, J. Liu, N. Wu, H. Jia and 2 other author(s). ICTA, page 1-2. IEEE, (2022)A 224-Gb/s Inverter-Based TIA with Interleaved Active-Feedback and Distributed Peaking in 28-nm CMOS for Silicon Photonic Receivers.S. Chen, J. Xue, L. Li, G. Li, Z. Zhang, J. Liu, L. Liu, B. Wang, Y. Li, and N. Qi. ICTA, page 198-199. IEEE, (2022)A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM.X. Shen, Z. Zhang, G. Li, Y. Chen, N. Qi, J. Liu, N. Wu, and L. Liu. ESSCIRC, page 257-260. IEEE, (2023)A 0.006-mm26-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop.Z. Zhang, X. Shen, Y. Li, G. Li, N. Qi, J. Liu, N. Wu, L. Liu, Y. Chen, and Z. Zhang. APCCAS, page 556-559. IEEE, (2022)

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