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Disambiguation of "Tamura, Hirotaka"

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A 30Gb/s 2x Half-Baud-Rate CDR.

, , , , , and . CICC, page 1-4. IEEE, (2019)

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Claudia Tamura

Ichiro Tamura

Hitoshi Tamura

Hirotaka Wakatsuki

Hirotaka Yoshida

 

Other publications of authors with the same name

A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS., , , , , , , , , and 5 other author(s). ISSCC, page 168-169. IEEE, (2010)Optimizing effective interconnect capacitance for FPGA power reduction., , and . FPGA, page 11-20. ACM, (2014)Charge recycling for power reduction in FPGA interconnect., , and . FPL, page 1-8. IEEE, (2013)An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection., , , , and . CICC, page 1-8. IEEE, (2013)A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process., , , , , , , , , and . CICC, page 131-134. IEEE, (2005)Jitter injection for on-chip jitter measurement in PI-based CDRs., , , and . CICC, page 1-4. IEEE, (2017)A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE., , , , and . CICC, page 1-4. IEEE, (2014)A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS., , , , , and . IEEE J. Solid State Circuits, 45 (6): 1091-1098 (2010)On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs., , , , and . IEEE J. Solid State Circuits, 50 (4): 845-855 (2015)A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 44 (12): 3580-3589 (2009)