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Disambiguation of "Kimura, Keiji"

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Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory.

, , , , , and . ACM Trans. Archit. Code Optim., 16 (2): 18:1-18:27 (2019)

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T Kimura

Keiji Kasai

Shuji Kimura

Keiji Sayama

Naoji Kimura

 

Other publications of authors with the same name

Android Video Processing System Combined with Automatically Parallelized and Power Optimized Code by OSCAR Compiler., , , , , and . J. Inf. Process., 24 (3): 504-511 (2016)Mixed Integer Nonlinear Program for Minimization of Akaike's Information Criterion., and . ICMS, volume 9725 of Lecture Notes in Computer Science, page 292-300. Springer, (2016)Compiler-support for Critical Data Persistence in NVM., , , , and . ACM Trans. Archit. Code Optim., 16 (4): 54:1-54:25 (2020)Reducing parallelizing compilation time by removing redundant analysis., , , , , , , , , and 1 other author(s). SEPS@SPLASH, page 1-9. ACM, (2016)An Android Systrace Extension for Tracing Wakelocks., and . CSE/EUC/DCABES, page 146-149. IEEE Computer Society, (2016)Software-cooperative power-efficient heterogeneous multi-core for media processing., , , , , , , , , and 1 other author(s). ASP-DAC, page 736-741. IEEE, (2008)An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler., , , , , , , , , and 6 other author(s). ISSCC, page 90-91. IEEE, (2008)Multigrain Parallelization for Model-Based Design Applications Using the OSCAR Compiler., , , , and . LCPC, volume 9519 of Lecture Notes in Computer Science, page 125-139. Springer, (2015)Detection of small cracks in the chain of a trolley conveyor with an infrared camera., , and . J. Intell. Manuf., 4 (4): 259-267 (1993)A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core., , , , , , , , , and 2 other author(s). IEICE Trans. Electron., 94-C (4): 663-669 (2011)