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Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic.

, , and . FPL, page 124-129. IEEE, (2005)

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On the feasibility of early routing capacitance estimation for FPGAs., , and . FPL, page 234-239. IEEE, (2007)A Digit-Serial Structure for Reconfigurable Multipliers., , and . FPL, volume 2147 of Lecture Notes in Computer Science, page 565-573. Springer, (2001)Fault tolerant methods for reliability in FPGAs., , and . FPL, page 415-420. IEEE, (2008)Combating process variation on FPGAS with a precise at-speed delay measurement method., , and . FPL, page 703-704. IEEE, (2008)Towards Affective Level Video Applications: A Novel FPGA-Based Video Arousal Content Modeling System., and . FPL, page 1-4. IEEE, (2006)Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design., , , and . FPT, page 54-61. IEEE Computer Society, (2009)Floating-point bitwidth analysis via automatic differentiation., , , , and . FPT, page 158-165. IEEE, (2002)Within-die delay variability in 90nm FPGAs and beyond., and . FPT, page 97-104. IEEE, (2006)Wave-pipelined intra-chip signaling for on-FPGA communications., , , and . Integr., 43 (2): 188-201 (2010)Customizable elliptic curve cryptosystems., , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (9): 1048-1059 (2005)