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A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits.

, , , , and . IEICE Trans. Inf. Syst., 91-D (3): 667-674 (2008)

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Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing., , , , , and . DAC, page 527-532. IEEE, (2007)Efficient Guided-Probe Fault Location Method for Sequential Circuits., , , and . IEICE Trans. Inf. Syst., 78-D (2): 122-129 (1995)Power supply noise and its reduction in at-speed scan testing.. ASICON, page 1-4. IEEE, (2015)Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains., , , , , , , and . ACM Trans. Design Autom. Electr. Syst., 17 (4): 48:1-48:16 (2012)A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application., , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (2): 287-291 (2019)Efficient Test Set Modification for Capture Power Reduction., , , , , , and . J. Low Power Electron., 1 (3): 319-330 (2005)Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns., , , , , and . J. Low Power Electron., 8 (2): 248-258 (2012)A Method to Detect Bit Flips in a Soft-Error Resilient TCAM., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (6): 1185-1196 (2018)Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (11): 1767-1776 (2009)LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 2938-2951 (2020)