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Disambiguation of "Spetalnick, Samuel D."

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A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking.

, , , , , , , , , , and . IEEE J. Solid State Circuits, 59 (1): 52-64 (January 2024)

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Samuel D Brody

Samuel Adler

Samuel Leipuner

Samuel Goldberg

Samuel Navon

 

Other publications of authors with the same name

A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range., , , , , , and . ISSCC, page 1-3. IEEE, (2022)Neuromorphic Swarm on RRAM Compute-in-Memory Processor for Solving QUBO Problem., , , , , and . DAC, page 1-6. IEEE, (2023)A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems., , , , , , and . ISSCC, page 1-3. IEEE, (2022)30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance., , , , , , , , , and 2 other author(s). ISSCC, page 482-484. IEEE, (2024)A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 59 (1): 52-64 (January 2024)A 2.38 MCells/mm2 9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation., , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking., , , , , , , , , and 1 other author(s). ISSCC, page 426-427. IEEE, (2023)