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A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking.

, , , , , , , , , , and . IEEE J. Solid State Circuits, 59 (1): 52-64 (January 2024)

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A 65nm 60mW Dual-Loop Adaptive Digital Beamformer with Optimized Sidelobe Cancellation and On-Chip DOA Estimation for mm-Wave Applications., , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)Live Demonstration: Hybrid RRAM and SRAM SoC for Fused Frame and Event Target Tracking., , , , , , and . ISCAS, page 1. IEEE, (2023)A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 59 (1): 52-64 (January 2024)A 2.38 MCells/mm2 9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation., , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 16b 1.62MS/s Calibration-free SAR ADC with 86.6dB SNDR utilizing DAC Mismatch Cancellation Based on Symmetry., , , and . A-SSCC, page 1-2. IEEE, (2020)A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking., , , , , , , , , and 1 other author(s). ISSCC, page 426-427. IEEE, (2023)