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Disambiguation of "Tsai, Ming-Chien"

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Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array.

, , , , , , , , , and . VLSI-DAT, page 1-4. IEEE, (2012)

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Schi-chien Tsai

Ming-Cheng Tsai

Ming-chien Chang

Tun-ming Tsai

Ming-tang Tsai

 

Other publications of authors with the same name

A full-synthesizable high-precision built-in delay time measurement circuit., and . ASP-DAC, page 123-124. IEEE, (2009)Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM., , , , , , , , , and 1 other author(s). APCCAS, page 116-119. IEEE, (2012)An all-digital bit transistor characterization scheme for CMOS 6T SRAM array., , , , , , , , , and . ISCAS, page 2485-2488. IEEE, (2012)Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (12): 3039-3047 (2010)Asymmetrical Write-assist for single-ended SRAM operation., , , , and . SoCC, page 101-104. IEEE, (2009)An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array., , , , , , , , , and 1 other author(s). VLSI-DAT, page 1-4. IEEE, (2012)Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array., , , , , , , , , and . VLSI-DAT, page 1-4. IEEE, (2012)High-Performance Low-Power Full-Swing Full Adder Cores with Output Driving Capability., , , and . APCCAS, page 614-617. IEEE, (2006)A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 47 (6): 1469-1482 (2012)An All-Digital High-Precision Built-In Delay Time Measurement Circuit., , and . VTS, page 249-254. IEEE Computer Society, (2008)