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Monolithic Integration of Quantum Resonant Tunneling Gate on a 22nm FD-SOI CMOS Process., , , , , , , , , and 2 other author(s). CoRR, (2021)Characterisation and Modelling of 22-nm FD-SOI Transistors Operating at Cryogenic Temperatures., , , , , , , , and . ICECS 2022, page 1-4. IEEE, (2022)Bias Generation and Calibration of CMOS Charge Qubits at 3.5 Kelvin in 22-nm FDSOI., , , , , , , , and . ESSCIRC, page 47-50. IEEE, (2021)Modelling of Electron Injection and Confinement in Cryogenic 22-nm FD-SOI Quantum Dot Arrays., , , , , , and . ICECS 2022, page 1-4. IEEE, (2022)Position-Based CMOS Charge Qubits for Scalable Quantum Processors at 4K., , , , , , , , , and 2 other author(s). ISCAS, page 1-5. IEEE, (2020)A Python-Verilog Toolbox for Modeling of a Hadamard Gate Based on Position-Based CMOS Qubits., , , , , and . ICECS, page 566-569. IEEE, (2019)A Mixed-Signal Control Core for a Fully Integrated Semiconductor Quantum Computer System-on-Chip., , , , , , , , , and 1 other author(s). ESSCIRC, page 125-128. IEEE, (2019)