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MulTCIM: Digital Computing-in-Memory-Based Multimodal Transformer Accelerator With Attention-Token-Bit Hybrid Sparsity.

F. Tu, Z. Wu, Y. Wang, W. Wu, L. Liu, Y. Hu, S. Wei, and S. Yin. IEEE J. Solid State Circuits, 59 (1): 90-101 (January 2024)

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Shaojun Lu

Shaojun Tong

Wei Wei

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A 1/2.5 inch VGA 400 fps CMOS Image Sensor With High Sensitivity for Machine Vision.R. Xu, W. Ng, G. Yuan, S. Yin, and S. Wei. IEEE J. Solid State Circuits, 49 (10): 2342-2351 (2014)An Energy-Efficient Reconfigurable Processor for Binary-and Ternary-Weight Neural Networks With Flexible Data Bit Width.S. Yin, P. Ouyang, J. Yang, T. Lu, X. Li, L. Liu, and S. Wei. IEEE J. Solid State Circuits, 54 (4): 1120-1136 (2019)PAGAN: A Phase-Adapted Generative Adversarial Networks for Speech Enhancement.P. Li, Z. Jiang, S. Yin, D. Song, P. Ouyang, L. Liu, and S. Wei. ICASSP, page 6234-6238. IEEE, (2020)TLIA: Efficient Reconfigurable Architecture for Control-Intensive Kernels with Triggered-Long-Instructions.L. Liu, J. Wang, J. Zhu, C. Deng, S. Yin, and S. Wei. IEEE Trans. Parallel Distributed Syst., 27 (7): 2143-2154 (2016)Exploiting Parallelism of Imperfect Nested Loops on Coarse-Grained Reconfigurable Architectures.S. Yin, X. Lin, L. Liu, and S. Wei. IEEE Trans. Parallel Distributed Syst., 27 (11): 3199-3213 (2016)Pattern-Based Dynamic Compilation System for CGRAs With Online Configuration Transformation.L. Liu, X. Man, J. Zhu, S. Yin, and S. Wei. IEEE Trans. Parallel Distributed Syst., 31 (12): 2981-2994 (2020)A High-performance Hardware Implementation of Saber Based on Karatsuba Algorithm.Y. Zhu, M. Zhu, B. Yang, W. Zhu, C. Deng, C. Chen, S. Wei, and L. Liu. IACR Cryptol. ePrint Arch., (2020)An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures.C. Wu, C. Deng, L. Liu, J. Han, J. Chen, S. Yin, and S. Wei. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (8): 1264-1277 (2015)Low Area-Overhead Low-Entropy Masking Scheme (LEMS) Against Correlation Power Analysis Attack.H. Huang, L. Liu, Q. Huang, Y. Chen, S. Yin, and S. Wei. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (2): 208-219 (2019)Memory Partitioning for Parallel Multipattern Data Access in Multiple Data Arrays.S. Yin, Z. Xie, C. Meng, P. Ouyang, L. Liu, and S. Wei. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (2): 431-444 (2018)

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Disambiguation of "Wei, Shaojun"

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MulTCIM: Digital Computing-in-Memory-Based Multimodal Transformer Accelerator With Attention-Token-Bit Hybrid Sparsity.

Please choose a person to relate this publication to

Shaojun Lu

Shaojun Tong

Wei Wei

Wei Wei

Wei Wei

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wei, Shaojun"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML MulTCIM: Digital Computing-in-Memory-Based Multimodal Transformer Accelerator With Attention-Token-Bit Hybrid Sparsity.

Please choose a person to relate this publication to

Shaojun Lu

Shaojun Tong

Wei Wei

Wei Wei

Wei Wei

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
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URL
DOI
BibTeX
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Chicago
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MulTCIM: Digital Computing-in-Memory-Based Multimodal Transformer Accelerator With Attention-Token-Bit Hybrid Sparsity.