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An Architecture Design Methodology for Minimal Total Power Consumption at Fixed Vdd and Vth.

C. Schuster, C. Piguet, J. Nagel, and P. Farine. J. Low Power Electron., 1 (1): 3-10 (2005)

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Jean-Luc Wolfender

Jean-Luc Rebière

Jean-Luc Boevé

Jean-Luc Wagner

Jean-Luc Régnier

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Maximum delay variation temperature-aware standard cell design.M. Pons, J. Nagel, and C. Piguet. ICECS, page 296-299. IEEE, (2012)Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures.C. Schuster, J. Nagel, C. Piguet, and P. Farine. PATMOS, volume 3254 of Lecture Notes in Computer Science, page 169-178. Springer, (2004)Low-power 32-bit dual-MAC 120 μW/MHz 1.0 V icyflex DSP/MCU core.C. Arm, S. Gyger, J. Masgonty, M. Morgan, J. Nagel, C. Piguet, F. Rampogna, and P. Volet. ESSCIRC, page 190-193. IEEE, (2008)Ultra low-power standard cell design using planar bulk CMOS in subthreshold operation.M. Pons, J. Nagel, D. Séverac, M. Morgan, D. Sigg, P. Rüedi, and C. Piguet. PATMOS, page 9-15. IEEE, (2013)Minimum Energy Point in Constant Frequency Designs under Adaptive Supply Voltage and Body Bias Adjustment in 55 nm DDC.C. Müller, M. Pons, D. Ruffieux, J. Nagel, S. Emery, A. Burg, S. Tanahashi, Y. Tanaka, and A. Takeuchi. PRIME, page 285-288. IEEE, (2019)Sub-threshold latch-based icyflex2 32-bit processor with wide supply range operation.M. Pons, T. Le, C. Arm, D. Séverac, J. Nagel, M. Morgan, and S. Emery. ESSCIRC, page 41-44. IEEE, (2016)Low-Power 32-bit Dual-MAC 120 µW/MHz 1.0 V icyflex1 DSP/MCU Core.C. Arm, S. Gyger, J. Masgonty, M. Morgan, J. Nagel, C. Piguet, F. Rampogna, and P. Volet. IEEE J. Solid State Circuits, 44 (7): 2055-2064 (2009)A multiscale morphological coprocessor for low-power face authentication.P. Stadelmann, J. Nagel, M. Ansorge, and F. Pellandini. EUSIPCO, page 1-4. IEEE, (2002)A low-complexity video coder based on the Discrete Walsh Hadamard Transform.R. Costantini, J. Bracamonte, G. Ramponi, J. Nagel, M. Ansorge, and F. Pellandini. EUSIPCO, page 1-4. IEEE, (2000)Energy-Autonomous MCU Operating in sub-VT Regime with Tightly-Integrated Energy-Harvester : A SoC for IoT smart nodes containing a MCU with minimum-energy point of 2.9pJ/cycle and a harvester with output power range from sub-µW to 4.32mW.J. Deng, J. Nagel, L. Zahnd, M. Pons, D. Ruffieux, C. Arm, P. Persechini, and S. Emery. ISLPED, page 1-4. IEEE, (2019)

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Disambiguation of "Nagel, Jean-Luc"

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An Architecture Design Methodology for Minimal Total Power Consumption at Fixed Vdd and Vth.

Please choose a person to relate this publication to

Jean-Luc Wolfender

Jean-Luc Rebière

Jean-Luc Boevé

Jean-Luc Wagner

Jean-Luc Régnier

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Nagel, Jean-Luc"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An Architecture Design Methodology for Minimal Total Power Consumption at Fixed Vdd and Vth.

Please choose a person to relate this publication to

Jean-Luc Wolfender

Jean-Luc Rebière

Jean-Luc Boevé

Jean-Luc Wagner

Jean-Luc Régnier

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

An Architecture Design Methodology for Minimal Total Power Consumption at Fixed Vdd and Vth.