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Neither more nor less: Optimizing thread-level parallelism for GPGPUs.

, , , and . PACT, page 157-166. IEEE Computer Society, (2013)

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Exploiting Latency and Error Tolerance of GPGPU Applications for an Energy-Efficient DRAM., and . DSN, page 362-374. IEEE, (2019)A Regression-based Model for End-to-End Latency Prediction for DNN Execution on GPUs., , and . ISPASS, page 343-345. IEEE, (2023)Design and Analysis of Soft-Error Resilience Mechanisms for GPU Register File., , , and . VLSID, page 409-414. IEEE Computer Society, (2017)Analyzing and Leveraging Shared L1 Caches in GPUs., , , , and . PACT, page 161-173. ACM, (2020)Controlled Kernel Launch for Dynamic Parallelism in GPUs., , , , , , , , and . HPCA, page 649-660. IEEE Computer Society, (2017)μC-States: Fine-grained GPU Datapath Power Management., , , , , , , , and . PACT, page 17-30. ACM, (2016)Zorua: A holistic approach to resource virtualization in GPUs., , , , , , , , and . MICRO, page 15:1-15:14. IEEE Computer Society, (2016)Practical Resilience Analysis of GPGPU Applications in the Presence of Single- and Multi-Bit Faults., , , and . IEEE Trans. Computers, 70 (1): 30-44 (2021)Analyzing and Leveraging Decoupled L1 Caches in GPUs., , , , and . HPCA, page 467-478. IEEE, (2021)Improving Multi-Application Concurrency Support Within the GPU Memory System., , , , , , , and . CoRR, (2017)