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Disambiguation of "Davis, James J."

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KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs.

, , , , , and . ACM Trans. Reconfigurable Technol. Syst., 11 (1): 2:1-2:22 (2018)

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James Davis

Katherine James

Audrein James

Michael James

Ammini James-Mammoottil

 

Other publications of authors with the same name

Reduced-precision Algorithm-based Fault Tolerance for FPGA-implemented Accelerators., and . ARC, volume 9625 of Lecture Notes in Computer Science, page 361-368. Springer, (2016)Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only)., , , , , and . FPGA, page 276. ACM, (2016)Early detection of emerging SARS-CoV-2 variants of interest for experimental evaluation., , , , , , , , and . Frontiers Bioinform., (2022)LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference., , , and . IEEE Trans. Computers, 69 (12): 1795-1808 (2020)Improvements to PATRIC, the all-bacterial Bioinformatics Database and Analysis Resource Center., , , , , , , , , and 18 other author(s). Nucleic Acids Res., 45 (Database-Issue): D535-D542 (2017)Enabling Binary Neural Network Training on the Edge., , , , , , , , and . ACM Trans. Embed. Comput. Syst., 22 (6): 105:1-105:19 (November 2023)Reducing Overheads for Fault-Tolerant Datapaths with Dynamic Partial Reconfiguration., and . FCCM, page 103. IEEE Computer Society, (2014)KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs., , , , , and . ACM Trans. Reconfigurable Technol. Syst., 11 (1): 2:1-2:22 (2018)Datapath fault tolerance for parallel accelerators., and . FPT, page 366-369. IEEE, (2013)Achieving low-overhead fault tolerance for parallel accelerators with dynamic partial reconfiguration., and . FPL, page 1-6. IEEE, (2014)