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Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers., and . FPGA, page 19-28. ACM, (2013)Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network., and . ACM Trans. Design Autom. Electr. Syst., 19 (2): 14:1-14:23 (2014)Faster FPGA Debug: Efficiently Coupling Trace Instruments with User Circuitry., , and . ARC, volume 8405 of Lecture Notes in Computer Science, page 73-84. Springer, (2014)Limitations of incremental signal-tracing for FPGA debug., and . FPL, page 49-56. IEEE, (2012)Scalable Signal Selection for Post-Silicon Debug., and . IEEE Trans. Very Large Scale Integr. Syst., 21 (6): 1103-1115 (2013)KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs., , , , , and . ACM Trans. Reconfigurable Technol. Syst., 11 (1): 2:1-2:22 (2018)KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications., , , , , and . IEEE Des. Test, 34 (6): 36-45 (2017)KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications., , , , , and . IWOCL, page 4:1. ACM, (2018)Invited Paper: RapidWright: Unleashing the Full Power of FPGA Technology with Domain-Specific Tooling., and . ICCAD, page 1-7. IEEE, (2023)Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices., , and . FCCM, page 45-52. IEEE Computer Society, (2013)