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Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures., , , , , , , , , and . VLSI Signal Processing, 9 (1-2): 49-65 (1995)System-Level Data-Flow Transformation Exploration and Power-Area Trade-offs Demonstrated on Video Codecs., , , and . VLSI Signal Processing, 18 (1): 39-50 (1998)Nonlinear transformations for high level regular array ASIC synthesis., , and . VLSI Signal Processing, 4 (4): 259-268 (1992)Performance Through Hierarchy in Static Timing Verification., , and . IFIP Congress (1), volume A-12 of IFIP Transactions, page 703-709. North-Holland, (1992)Static Timing Analysis of Dynamically Sensitizable Paths., , and . DAC, page 568-573. ACM Press, (1989)Loop Optimization in Register-Transfer Scheduling for DSP-Systems., , and . DAC, page 826-831. ACM Press, (1989)Formalized three-layer system-level model and reuse methodology for embedded data-dominated applications., , , and . IEEE Trans. Very Large Scale Integr. Syst., 8 (2): 207-216 (2000)Background memory area estimation for multidimensional signal processing systems., , and . IEEE Trans. Very Large Scale Integr. Syst., 3 (2): 157-172 (1995)A Proof of the Nonrestoring Division Algorithm and its Implementation on an ALU., , and . Formal Methods Syst. Des., 4 (1): 5-31 (1994)Transformation of Nested Loops with Modulo Indexing to Affine Recurrences., , , and . Parallel Process. Lett., (1994)