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Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip.

P. Chen, D. Kadetotad, Z. Xu, A. Mohanty, B. Lin, J. Ye, S. Vrudhula, J. sun Seo, Y. Cao, and S. Yu. DATE, page 854-859. ACM, (2015)

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Pai Tsang Chen

Yu Chen

Other publications of authors with the same name

Design of Resistive Synaptic Array for Implementing On-Chip Sparse Learning.P. Chen, L. Gao, and S. Yu. IEEE Trans. Multi Scale Comput. Syst., 2 (4): 257-264 (2016)Low-temperature process in growing carbon nanotube.S. Chang, T. Lin, and C. Pai. Microelectron. J., 38 (6-7): 657-662 (2007)Technological Benchmark of Analog Synaptic Devices for Neuroinspired Architectures.P. Chen, and S. Yu. IEEE Des. Test, 36 (3): 31-38 (2019)Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing.P. Chen, J. sun Seo, Y. Cao, and S. Yu. ICCAD, page 15. ACM, (2016)Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity.Z. Xu, A. Mohanty, P. Chen, D. Kadetotad, B. Lin, J. Ye, S. Vrudhula, S. Yu, J. sun Seo, and Y. Cao. BICA, volume 41 of Procedia Computer Science, page 126-133. Elsevier, (2014)Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning.D. Kadetotad, Z. Xu, A. Mohanty, P. Chen, B. Lin, J. Ye, S. Vrudhula, S. Yu, Y. Cao, and J. sun Seo. BioCAS, page 536-539. IEEE, (2014)Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design.S. Zuloaga, R. Liu, P. Chen, and S. Yu. ISCAS, page 193-196. IEEE, (2015)Partition SRAM and RRAM based synaptic arrays for neuro-inspired computing.P. Chen, and S. Yu. ISCAS, page 2310-2313. IEEE, (2016)Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array.P. Chen, Z. Li, and S. Yu. IEEE Trans. Very Large Scale Integr. Syst., 24 (12): 3460-3467 (2016)MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System.L. Xia, B. Li, T. Tang, P. Gu, P. Chen, S. Yu, Y. Cao, Y. Wang, Y. Xie, and H. Yang. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (5): 1009-1022 (2018)

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Disambiguation of "Chen, Pai-Yu"

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Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip.

Please choose a person to relate this publication to

Pai Tsang Chen

Pai Tsang Chen

Pai Tsang Chen

Yu Chen

Yu Chen

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chen, Pai-Yu"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip.

Please choose a person to relate this publication to

Pai Tsang Chen

Pai Tsang Chen

Pai Tsang Chen

Yu Chen

Yu Chen

Other publications of authors with the same name

Disambiguation

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URL
DOI
BibTeX
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Chicago
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Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip.