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Disambiguation of "Yu, Shimeng"

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Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip.

, , , , , , , , , and . DATE, page 854-859. ACM, (2015)

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Shimeng Chen

Yu-Ting Yu

Yu-Yu Su

Sze-Man Yu

Metal complexes with enolatoimine ligands for controlled olefin polymerizations. Uni Konstanz, (2009)

Zhejun Yu

 

Other publications of authors with the same name

Large-Scale Neuromorphic Spiking Array Processors: A quest to mimic the brain., , , , , , , , , and 5 other author(s). CoRR, (2018)Compute-in-Memory for AI: From Inference to Training.. VLSI-DAT, page 1. IEEE, (2020)Impact of Selector Devices in Analog RRAM-Based Crossbar Arrays for Inference and Training of Neuromorphic System., and . IEEE Trans. Very Large Scale Integr. Syst., 27 (9): 2205-2212 (2019)Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing., , , , , , and . IRPS, page 1-7. IEEE, (2021)Mitigating Adversarial Attack for Compute-in-Memory Accelerator Utilizing On-chip Finetune., , and . NVMSA, page 1-6. IEEE, (2021)Architectural Design of 3D NAND Flash based Compute-in-Memory for Inference Engine., , , and . MEMSYS, page 77-85. ACM, (2020)NeuroSim Validation with 40nm RRAM Compute-in-Memory Macro., , , , and . AICAS, page 1-4. IEEE, (2021)Compute-in-RRAM with Limited On-chip Resources., , and . AICAS, page 1-4. IEEE, (2021)Enabling Long-Term Robustness in RRAM-based Compute-In-Memory Edge Devices., , and . ISCAS, page 1-5. IEEE, (2023)A monolithic 3D design technology co-optimization with back-end-of-line oxide channel transistor., , and . NANOARCH, page 6:1-6:6. ACM, (2022)