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Disambiguation of "Tyszer, Jerzy"

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Design for low test pattern counts.

, , , , , , and . DAC, page 136:1-136:6. ACM, (2015)

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Weyman Jerzy

Szynka Jerzy

Jerzy Blaszczyk

Jerzy Cieslik

Jerzy Krzeczowski

 

Other publications of authors with the same name

Test Data Decompression for Multiple Scan Designs with Boundary Scan., , and . IEEE Trans. Computers, 47 (11): 1188-1200 (1998)Combinatorial Approach to Multiple Contact Faults Coverage in Programmable Logic Arrays., and . IEEE Trans. Computers, 34 (6): 549-553 (1985)Recursive Pseudoexhaustive Test Pattern Generation., and . IEEE Trans. Computers, 42 (12): 1517-1521 (1993)X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (1): 147-159 (2008)On Compaction Utilizing Inter and Intra-Correlation of Unknown States., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (1): 117-126 (2010)Automated synthesis of phase shifters for built-in self-testapplications., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (10): 1175-1188 (2000)Testing of three-stage switching networks for coupling faults.. IEEE Trans. Commun., 40 (2): 413-422 (1992)Trimodal Scan-Based Test Paradigm., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (3): 1112-1125 (2017)A Lightweight True Random Number Generator for Root of Trust Applications., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (9): 2815-2825 (September 2023)On New Class of Test Points and Their Applications., , and . ITC, page 1-9. IEEE, (2018)