( en | de | ru )

 

Disambiguation of "Zawada, Justyna"

Author of the publication

copydeleteadd this publication to your clipboard
Design for low test pattern counts.

, , , , , , and . DAC, page 136:1-136:6. ACM, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Anna Zawada

Justyna Wierzchowska

Justyna Krachulec

Justyna Siwy

Justyna Zander

 

Other publications of authors with the same name

Embedded deterministic test points for compact cell-aware tests., , , , , , , , , and . ITC, page 1-8. IEEE, (2015)Logic BIST With Capture-Per-Clock Hybrid Test Points., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (6): 1028-1041 (2019)Hardware Protection via Logic Locking Test Points., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (12): 3020-3030 (2018)Full-scan LBIST with capture-per-cycle hybrid test points., , , , , and . ITC, page 1-9. IEEE, (2017)On New Test Points for Compact Cell-Aware Tests., , , , , , , , , and . IEEE Des. Test, 33 (6): 7-14 (2016)Quality assurance in memory built-in self-test tools., , , , , and . DDECS, page 39-44. IEEE Computer Society, (2014)Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations., , , , , , , , , and 1 other author(s). ITC, page 1-10. IEEE, (2020)On New Class of Test Points and Their Applications., , and . ITC, page 1-9. IEEE, (2018)Efficient Test Compression Configuration Selection., , , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (7): 2323-2336 (2022)On Test Points Enhancing Hardware Security., , , , and . ATS, page 61-66. IEEE Computer Society, (2016)