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On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression.

, , , , , and . VLSI Design, page 279-284. IEEE Computer Society, (2013)

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Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard., , , , , , , , , and 6 other author(s). ITC, page 1-9. IEEE Computer Society, (2008)A circular pipeline processing based deterministic parallel test pattern generator., , , and . ITC, page 1-8. IEEE Computer Society, (2013)Test compression and logic BIST at your fingertips., , , , and . ITC, page 2. IEEE Computer Society, (2005)Logic BIST Architecture for System-Level Test and Diagnosis., , , , , , , , , and 5 other author(s). Asian Test Symposium, page 21-26. IEEE Computer Society, (2009)On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST., , , , , , and . Asian Test Symposium, page 19-24. IEEE Computer Society, (2013)VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG., , , , , , and . IEEE Des. Test Comput., 25 (2): 122-130 (2008)Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains., , , , , , , , , and 2 other author(s). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (3): 455-463 (2011)Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding., , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (3): 942-953 (2017)High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme., , , , , , , and . IEICE Trans. Inf. Syst., 93-D (1): 2-9 (2010)Test data compression based on clustered random access scan., , , , , , , , and . ATS, page 231-236. IEEE, (2006)