Author of the publication

VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG.

, , , , , , and . IEEE Des. Test Comput., 25 (2): 122-130 (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing., , and . ACM Trans. Design Autom. Electr. Syst., 17 (2): 18:1-18:24 (2012)Self-Testing of Embedded RAMs., and . ITC, page 148-156. IEEE Computer Society, (1984)Turbo1500: Core-Based Design for Test and Diagnosis., , , , , , , , , and 5 other author(s). IEEE Des. Test Comput., 26 (1): 26-35 (2009)A Novel ATPG Method for Capture Power Reduction during Scan Testing., , , , , , and . IEICE Trans. Inf. Syst., 90-D (9): 1398-1405 (2007)CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing., , , , , , , and . ATS, page 397-402. IEEE Computer Society, (2008)At-Speed Logic BIST for IP Cores., , , , , , , , and . DATE, page 860-861. IEEE Computer Society, (2005)Low-capture-power test generation for scan-based at-speed testing., , , , , , and . ITC, page 10. IEEE Computer Society, (2005)GPU-based timing-aware test generation for small delay defects., , , , , and . ETS, page 1-2. IEEE, (2014)Luncheon Speaker: "Introduction to SoC testing".. SoCC, page 256-257. IEEE, (2011)A Hybrid Design of Maximum-Length Sequence Generators., and . ITC, page 38-47. IEEE Computer Society, (1986)