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Disambiguation of "Pamarti, Sudhakar"

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A Spur Elimination Technique for Phase Interpolation-Based Fractional-N PLLs.

, and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (6): 1639-1647 (2008)

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Sudhakar Peddireddi

Padhmanand Sudhakar

Sudhakar Motiram Chaudhari

Yamini Sudhakar Avadhut

 

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A precisely-timed energy injection technique achieving 58/10/2μs start-up in 1.84/10/50MHz crystal oscillators., and . CICC, page 1-4. IEEE, (2017)A 3×3.8Gb/s four-wire high speed I/O link based on CDMA-like crosstalk cancellation., , and . CICC, page 121-124. IEEE, (2009)A temperature-to-digital converter for a MEMS-based programmable oscillator with better than ±0.5ppm frequency stability., , , , , , , , , and 3 other author(s). ISSCC, page 206-208. IEEE, (2012)Time-varying circuit approaches for software defined and cognitive radio applications., , , and . ISOCC, page 155-156. IEEE, (2016)Worst case timing jitter and amplitude noise in differential signaling., , , , and . ISQED, page 40-46. IEEE Computer Society, (2009)23.8 A 34V charge pump in 65nm bulk CMOS technology., , , and . ISSCC, page 408-409. IEEE, (2014)A Sub-50fs-Jitter Sub-Sampling PLL with a Harmonic-Enhanced 30-GHz-Fundemental Class-C VCO in 0.18µm SiGe BiCMOS., , , , , , , and . ESSCIRC, page 435-438. IEEE, (2021)Filtering of subtractive discrete dither in quantizers: Some new results., and . ICASSP, page 5790-5794. IEEE, (2013)A Spur Elimination Technique for Phase Interpolation-Based Fractional-N PLLs., and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (6): 1639-1647 (2008)RF digital predistorter implementation using polynomial optimization., , and . MWSCAS, page 981-984. IEEE, (2014)