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Disambiguation of "Daly, Barry"

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A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface.

, , , , , , , , , , , and . IEEE J. Solid State Circuits, 49 (4): 1048-1062 (2014)

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Kieran Daly

Marwa Daly

Hesham Daly

Ulvi Dalyan

Georg Barry

 

Other publications of authors with the same name

A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 50 (4): 814-827 (2015)A 6.4Gb/s near-ground single-ended transceiver for dual-rank DIMM memory interface systems., , , , , , , , , and 6 other author(s). ISSCC, page 306-307. IEEE, (2013)A 40-Gb/s serial link transceiver in 28-nm CMOS technology., , , , , , , , , and 4 other author(s). VLSIC, page 1-2. IEEE, (2014)A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering., , , , , , , , , and 4 other author(s). VLSIC, page 1-2. IEEE, (2014)A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 49 (4): 1048-1062 (2014)A 32mW 7.4Gb/s protocol-agile source-series-terminated transmitter in 45nm CMOS SOI., , , , , , and . ISSCC, page 370-371. IEEE, (2010)Elastic registration using 3D ChainMail: application to virtual colonoscopy., , and . Medical Imaging: Image Processing, volume 6144 of SPIE Proceedings, page 61442Y. SPIE, (2006)A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching., , , , , , , , , and . CICC, page 1-4. IEEE, (2012)Use of a Thin-Section Archive and Enterprise 3D Software for Long-Term Storage of Thin-Slice CT Data Sets., , , and . J. Digital Imaging, 19 (S-1): 84-88 (2006)A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 49 (1): 127-139 (2014)